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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 23: GTX Transceiver Transmitter Switching Characteristics
F GTXTX
Symbol
Description
Serial data rate range
Condition
Min
0.480
Typ
–
Max
F GTXMAX
Units
Gb/s
T RTX
T FTX
T LLSKEW
TX Rise time
TX Fall time
TX lane-to-lane
skew (1)
20%–80%
80%–20%
–
–
–
120
120
–
–
–
350
ps
ps
ps
V TXOOBVDPP
T TXOOBTRANSITION
Electrical idle amplitude
Electrical idle transition time
–
–
–
–
15
75
mV
ns
TJ 6.5
DJ 6.5
TJ 5.0
DJ 5.0
TJ 4.25
DJ 4.25
TJ 3.75
DJ 3.75
TJ 3.125
DJ 3.125
TJ 3.125L
DJ 3.125L
TJ 2.5
DJ 2.5
TJ 1.25
DJ 1.25
TJ 600
DJ 600
TJ 480
DJ 480
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
Total Jitter (2)(3)
Deterministic Jitter (2)(3)
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s (4)
2.5 Gb/s (5)
1.25 Gb/s (6)
600 Mb/s
480 Mb/s
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.33
0.17
0.33
0.15
0.33
0.14
0.34
0.16
0.2
0.1
0.35
0.16
0.20
0.08
0.15
0.06
0.1
0.03
0.1
0.03
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Notes:
1.
2.
3.
4.
5.
6.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
All jitter values are based on a bit-error ratio of 1e -12 .
PLL frequency at 1.5625 GHz and OUTDIV = 1.
PLL frequency at 2.5 GHz and OUTDIV = 2.
PLL frequency at 2.5 GHz and OUTDIV = 4.
DS152 (v3.6) March 18, 2014
Product Specification
15
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